PWMEN3=EM3, PWMEN2=EM2, PWMEN0=EM0, PWMEN1=EM1
PWM Control Register (PWMCON). The PWMCON enables PWM mode for the external match pins CT16B0_MAT[2:0].
| PWMEN0 | PWM channel0 enable 0 (EM0): CT16Bn_MAT0 is controlled by EM0. 1 (PWMMODE): PWM mode is enabled for CT16Bn_MAT0. |
| PWMEN1 | PWM channel1 enable 0 (EM1): CT16Bn_MAT1 is controlled by EM1. 1 (PWMMODE): PWM mode is enabled for CT16Bn_MAT1. |
| PWMEN2 | PWM channel2 enable 0 (EM2): Match channel 2 or pin CT16B0_MAT2 is controlled by EM2. Match channel 2 is not pinned out on timer 1. 1 (PWMMODE): PWM mode is enabled for match channel 2 or pin CT16B0_MAT2. |
| PWMEN3 | PWM channel3 enable Note: It is recommended to use match channel 3 to set the PWM cycle because it is not pinned out. 0 (EM3): Match channel 3 match channel 3 is controlled by EM3. 1 (PWMMODE): PWM mode is enabled for match channel 3match channel 3. |
| RESERVED | Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. |